The present invention relates to a signal processing apparatus and method and a provision medium and, more particularly, to a signal processing apparatus and method and a provision medium arranged to enable detection of a unique pattern with high accuracy.
Regular digital multichannel broadcasting using a communication satellite (hereinafter referred to as xe2x80x9cCSxe2x80x9d) has been started in Japan and related various services have also been started or are about to be started. With respect to broadcasts using broadcasting satellites (hereinafter referred to as xe2x80x9cBSxe2x80x9d), a plan for a digital broadcasting service using the BS4 scheduled to be put into the sky has been reported in the Radio Regulatory Council.
Because BSs have power larger than that of CSs, use of a modulation system having a transmission efficiency higher than that of the quadrature phase shift keying (QPSK) system conventionally used with CSs is being studied. To ensure compatibility with other media such as CSs, ground waves and cable networks, transmission of a bit stream based on the socalled transport stream (hereinafter referred to as xe2x80x9cTSxe2x80x9d) prescribed in MPEG (Moving Picture Experts Group) 2 has been proposed. The TS is formed of 188-byte packets containing one-byte units of sync bytes. Since a Reed-Solomon code (hereinafter referred to as xe2x80x9cRS codexe2x80x9d) formed by adding 16-byte parity for error correction to the TS is being used in cable digital broadcasting and so on, use of the (204, 188) RS code formed on the TS has also been proposed for BS digital broadcasting.
With this background, in documents already made public: xe2x80x9cEisei ISDB niokeru saidaidensoyoryo to eiseihosopuran eno tekiyo (Maximum transmission capacity in satellite ISDB and application to satellite broadcasting plan)xe2x80x9d, the Journal of Denshijohotsushin Gakkai (the Institute of Electronics, Information and Communication Engineers), Vol.J79-B-II No.7, xe2x80x9cEisei ISDB densohoshiki no kento (Study of satellite ISDB transmission system)xe2x80x9d, a technical report from Eizojohomedia Gakkai (the Institute of Image Information and Television), Vol.21 BCS-97-12, etc., methods are proposed in which a convolutionally coded BPSK (binary phase shift keying) signal, a QPSK (quadrature phase shift keying) signal, or a trellis-coded 8PSK (octaphase shift keying) signal is used as the main signal portion for payload information other than the sync portion in the (204, 188) RS-coded TS, and in which transmission information such as information about the modulation method, the code rate, etc., (hereinafter referred to as xe2x80x9ctransmission multiplexing configuration control (TMSS) informationxe2x80x9d) is transmitted in a BPSK signal by using the sync portion of the TS.
FIG. 7 shows the configuration of an example of a satellite digital broadcast receiver with which one of the methods described in the above-mentioned documents is used. A broadcast signal from a BS, e.g., a BPSK-modulated signal is captured by an antenna 1 and frequency-converted into an intermediate frequency signal by an unillustrated frequency conversion circuit incorporated in the antenna 1, and this intermediate frequency signal is supplied to a tuner 2. After controlling the antenna 1 to receive the broadcast signal from the BS, the tuner 2 reads a signal of a program designated by a predetermined operation, and outputs the read signal to a second intermediate frequency circuit 3. The second intermediate frequency circuit 3 shapes the spectrum of the signal input from the tuner 2 and performs predetermined amplification of the signal, and outputs the signal to multipliers 5-1 and 5-2 of an orthogonal demodulation circuit 4.
Each of the multipliers 5-1 and 5-2 of the orthogonal demodulation circuit 4 multiplies together the BPSK-modulated signal input from the second intermediate frequency circuit 3 and one of two carriers input from a carrier reproduction circuit 11 in phase-orthogonal to each other, and outputs a multiplication result to the carrier reproduction circuit 11, to a unique word detection circuit 120, to a TMCC decoder 12 and to an error correcting circuit 13 via low-pass filters (LPF) 6-1 and 6-2.
The unique word detection circuit 120 detects from the input signal a unique pattern formed as a frame sync signal, and outputs a detection result to the TMCC decoder 12. The TMCC decoder 12 decodes a TMCC signal in the input signal and outputs a decoding result to the carrier reproduction circuit 11 and to the error correcting circuit 13.
The carrier reproduction circuit 11 is supplied with a signal representing a phase error of the carriers which occurs when the TMCC decoder decodes the TMCC signal. The carrier reproduction circuit 11 reproduces two orthogonal carriers according to the supplied signal and outputs the reproduced carriers to the orthogonal demodulation circuit 4. The error correcting circuit 13 has unillustrated components: a Viterbi decoder, a Reed-Solomon decoder and an interleave circuit. The error correcting circuit 13 corrects a transmission channel error in the input main signal (QPSK signal) based on the TMCC signal from the TMCC decoder 12, and outputs the corrected signal.
FIG. 8 shows the configuration of an example of the unique word detection circuit 120. The unique word detection circuit 120 is formed by a differential demodulation circuit 121 and a unique word differential pattern detection circuit 122. A register 123-1 of the differential demodulation circuit 121 delays, for example, the sync signal of the BPSK signal input from the orthogonal demodulation circuit 4 by a predetermined time period (corresponding to one symbol), and outputs the delayed signal to a multiplier 124-1. The multiplier 124-1 multiplies together the signal (sync signal) directly input from the orthogonal demodulation circuit 4 and the signal delayed by the predetermined time period and supplied from the register 123-1, and outputs a multiplication result to an adder 125.
The register 123-2 of the differential demodulation circuit 121 also delays, for example, the orthogonal signal of the BPSK signal input from the orthogonal demodulation circuit 4 by the predetermined time period (corresponding to one symbol), and outputs the delayed signal to a multiplier 124-2. The multiplier 124-2 multiplies together the signal (orthogonal signal) directly input from the orthogonal demodulation circuit 4. and the signal delayed by the predetermined time period and supplied from the register 123-2, and outputs a multiplication result to the adder 125.
The adder 125 adds together the signal input from the multiplier 124-1 and the signal input from the multiplier 124-2, and supplies an addition result to a binalization circuit 126 of the unique word differential pattern detection circuit 122.
The binalization circuit 126 of the unique word differential pattern detection circuit 122 binalizes the signal input from the adder 125 of the differential demodulation circuit 121 by a data width of one bit, and outputs the binalized signal to a register 127-1. The register 127-1 stores the signal from the binalization circuit 126 and outputs the stored signal to a register 127-2 and to an exclusive-OR circuit (hereinafter referred to as xe2x80x9cEX-ORxe2x80x9d) 128-1 in the next stage in synchronization with a clock. The EX-OR 128-1 performs exclusive-OR processing of the signal from the register 127-1 and a predetermined signal S1 separately input, and outputs a processing result to a NOR circuit 130.
Similarly, each of registers 127-2 to 127-(nxe2x88x921) records the input signal and outputs the recorded signal to one of the registers 127-3 to 127-(nxe2x88x921) and to one of EX-ORs 128-1 to 128-(nxe2x88x921) in the next stage in synchronization with the clock. The register 127-(nxe2x88x921) outputs the stored signal to the EX-OR 128-(nxe2x88x921). Each of the EX-ORs 128-1 to 128-(nxe2x88x921) performs exclusive-OR processing of the input signal and outputs a processing result to the NOR circuit 130. The NOR circuit 130 performs NOR processing of the signals input from the EX-ORs 128-1 to 128-(nxe2x88x921), and outputs a processing result to the TMCC decoder 12.
In the case of this arrangement, since the received signal has a BPSK signal constellation, differential demodulation results are obtained as real numbers. Therefore, the differential demodulation circuit 121 is formed by two registers 123-1 and 123-2 for delaying the real and imaginary parts, respectively, by the one-symbol period, multipliers 124-1 and 124-2 each for multiplying together the real or imaginary part and the signal obtained by delaying the real or imaginary part by the one-symbol period, and adder 125 for adding together multiplication results from these multipliers.
Ordinarily, if an n-bit unique word is used, an (nxe2x88x921)-bit unique differential pattern is obtained. Accordingly, the unique word differential pattern detection circuit 122 has registers 127-1 to 127-(nxe2x88x921) corresponding to nxe2x88x921 bits. The exclusive-ORs of the corresponding bits of the outputs from these registers and the known (nxe2x88x921)-bit unique word differential pattern s1 to s(nxe2x88x921) are calculated by the EX-ORs 128-1 to 128-(nxe2x88x921). When the input signal is the unique word, the contents of the registers 127-1 to 127-(nxe2x88x921) and the unique word differential pattern s1 to s(nxe2x88x921) coincide with each other and a logical value xe2x80x9c0xe2x80x9d is output from the EX-ORs 128-1 to 128-(nxe2x88x921). The NOR circuit 130 recognizes this result to output a logical value xe2x80x9c1xe2x80x9d.
The TMCC decoder 12 decodes the TMCC signal when it obtains xe2x80x9c1xe2x80x9d from the NOR circuit 130 of the unique word detection circuit 120.
Because of the above-described detection of a unique word based on the difference between the phase of the two signals one of which precedes the other (differential demodulation using a noise-containing received signal used as a reference signal), a transmission channel error condition of one of the two signals influences the other signal. Mainly for this reason, the carrier to noise power ratio (C/N) is low. Moreover, since a known sync pattern, e.g., a unique word differential pattern is detected from the signals demodulated by hard-decision demodulation (demodulation by the orthogonal demodulation circuit), the detection accuracy is not reliably high. For the above-described reasons, it is difficult to accurately detect a unique word, and the necessary detection time is disadvantageously long.
In view of the above-described circumstances, an object of the present invention is to provide a signal processing apparatus and method and a provision medium arranged to enable detection of a unique pattern in a short time with high accuracy.
To achieve this object, according to one aspect of the present invention, there is provided a signal processing apparatus comprising calculation means for calculating a value representing a correlation between an input signal and a reference signal, and comparison means for comparing the calculated correlation value with a predetermined threshold value.
According to another aspect of the present invention, there is provided a signal processing apparatus comprising the step of calculating a value representing a correlation between an input signal and a reference signal, and the step of comparing the calculated correlation value with a predetermined threshold value.
According to still another aspect of the present invention, there is provided a provision medium for providing a program for executing a process comprising the step of calculating a value representing a correlation between an input signal and a reference signal, and the step of comparing the calculated correlation value with a predetermined threshold value.